Senior Layout Engineer

### Role Location: Zürich, Switzerland  Seniority: 5+ years (custom analog/SRAM/custom-digital layout) Own transistor-level and block-level custom layout for mixed-signal, SRAM, and custom-digital IP that powers our compute-in-memory SRAM (ComputeRAM®). You will plan floorplans, implement device-level layouts with production-grade matching/guarding, close DRC/LVS/PEX on advanced nodes down to 4 nm and below, and collaborate tightly with custom-design, digital, and PD/STA teams to hit aggressive PPA, yield, and reliability targets. You will bridge classic analog techniques (common-centroid/interdigitation, shielding, isolation) with FinFET/FDSOI rules, multi-patterning/EUV constraints, and modern DFM practices. ### What you’ll do * Plan & implement full-custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays. * Drive and provide feedback to the design team to converge on the most power-aware design layout possible. * Interface & integrate: align with schematic owners on constraints; define pins/abstracts, LEF views, keep-outs, and tiling for memory-like macros; coordinate with MBIST/scan wrappers and test hooks. * Automate & document: maintain checklists, templates, and layout guidelines; script repetitive tasks (TCL, Python) ### Outcomes (first 18 months) * Tape-in and silicon of one or more custom blocks or macros with clean DRC/LVS/PEX and correlated post-silicon parasitics (report + lessons-learned). ### Requirements * 5+ years in custom layout for analog/SRAM/custom-digital IP; strong ownership from floorplan to sign-off. * Demonstrated quality on sub-28 nm nodes; practical know-how for FinFET/FDSOI, multi-patterning/EUV constraints, coloring. * Solid analog layout techniques: common-centroid, interdigitation, current-mirror symmetry, matched routing, shielding/guard rings, substrate noise isolation. * Working grasp of timing/IR/EM implications of layout; ability to read extraction/timing reports and iterate with designers/PD/STA. * Clear communication, rigorous documentation, and a collaboration mindset across custom design, digital, and backend teams. ### Nice to have * Experience with SRAM arrays/periphery, redundancy/repair hooks, MBIST/scan routing constraints. * TCL/Python for layout automation and report generation. * DFM/DFY exposure * ESD/latch-up design practice; EM/IR sign-off collaboration at the macro level. * Comfort producing LEF and working with integration/floorplanning teams on macro delivery. ### Apply Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer) ### Interview flow (indicative) 1.  30-min intro with HR (role/context) 2.  First Technical deep dive 3.  Second Technical Deep Dive 4.  (Optional) Third Technical Deep Dive 5.  Systems/product conversation with management Your CV I agree to the terms and conditions as described in the Privacy Notice Send me informations about new products and company updates Indiquez votre site